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? semiconductor components industries, llc, 2010 may, 2010 ? rev. 22 1 publication order number: ncv8504/d ncv8504 series micropower 400 ma ldo linear regulators with delay, adjustable reset , and general use comparator the ncv8504 is a family of precision micropower voltage regulators. their output current capability is 400 ma. the family has output voltage options for adjustable, 2.5 v, 3.3 v and 5.0 v. the output voltage is accurate within 2.0% with a maximum dropout voltage of 0.6 v at 400 ma. low quiescent current is a feature drawing only 100 a with a 100 a load. this part is ideal for any and all battery operated microprocessor equipment. microprocessor control logic includes an active reset (with delay). the active reset circuit operates correctly at an output voltage as low as 1.0 v. the reset function is activated during the power up sequence or during normal operation if the output voltage drops below the regulation limits. the reset threshold voltage can be decreased by the connection of external resistor divider to r adj lead. the general use comparator (flag /monitor) is referenced to a temperature stable voltage and provides 1 ma of drive current at its open collector output. the regulator is protected against reverse battery, short circuit, and thermal overload conditions. the device can withstand load dump transients making it suitable for use in automotive environments. the device has also been optimized for emc conditions. features ? output voltage options: adjustable, 2.5 v, 3.3 v, 5.0 v ? 2.0% output ? low 100 a quiescent current ? fixed or adjustable output voltage ? active reset ? adjustable reset ? 400 ma output current capability ? fault protection ? +60 v peak transient voltage ? ? 15 v reverse voltage ? short circuit ? thermal overload ? general use comparator ? ncv prefix for automotive and other applications requiring site and change control ? aec qualified ? ppap capable ? these are pb ? free devices see detailed ordering and shipping information in the package dimensions section on p age 11 of this data sheet. ordering information x = voltage ratings as indicated below: a = adjustable 2 = 2.5 v 3 = 3.3 v 5 = 5.0 v a = assembly location wl = wafer lot yy = year ww = work week g = pb ? free device http://onsemi.com marking diagram soic 16 lead wide body exposed pad pdw suffix case 751ag 1 16 ncv8504x awlyywwg 1 16
ncv8504 series http://onsemi.com 2 pin connections fixed output adjustable output r adj mon 1 16 delay v in nc nc nc nc gnd nc nc nc reset v out flag v adj r adj mon 1 16 delay v in nc nc nc nc gnd nc nc nc reset v out flag sense v out gnd v in r adj ncv8504 33 f 5.1 k r rst reset 10 f microprocessor delay c delay v bat v dd flag figure 1. application diagram mon r flg 5.1 k v adj (adjustable output only) i/o i/o sense (fixed output only) monitor (v o ) i q
ncv8504 series http://onsemi.com 3 maximum ratings* rating value unit v in (dc) ? 15 to 45 v peak transient voltage (46 v load dump @ v in = 14 v) 60 v operating voltage 45 v v out (dc) ? 0.3 to 16 v voltage range (reset , flag , r adj , delay) ? 0.3 to 10 v input voltage range mon v adj ? 0.3 to 10 ? 0.3 to 16 v v esd susceptibility (human body model) (machine model) 4.0 200 kv v junction temperature, t j ? 40 to +150 c storage temperature, t s ? 55 to 150 c package thermal resistance, sow ? 16 e pad: junction ? to ? case, r jc junction ? to ? ambient, r ja 16 57 c/w c/w lead temperature soldering: reflow: (smd styles only) (note 1) 260 peak (note 2) c 1. 150 second maximum above 217 c. 2. ? 5 c/+0 c allowable conditions. *the maximum package power dissipation must be observed. ?during the voltage range which exceeds the maximum tested voltage of v in , operation is assured, but not specified. wider limits may apply. thermal dissipation must be observed closely. electrical characteristics (i out = 1.0 ma, ? 40 c t j 150 c; v in = dependent on voltage option (note 3); unless otherwise specified.) characteristic test conditions min typ max unit output stage output voltage for 2.5 v option (v o ) 6.5 v < v in < 16 v, 1.0 ma i out 400 ma 4.5 v < v in < 26 v , 1.0 ma i out 400 ma 2.450 2.425 2.5 2.5 2.550 2.575 v v output voltage for 3.3 v option (v o ) 7.3 v < v in < 16 v, 1.0 ma i out 400 ma 4.5 v < v in < 26 v , 1.0 ma i out 400 ma 3.234 3.201 3.3 3.3 3.366 3.399 v v output voltage for 5.0 v option (v o ) 9.0 v < v in < 16 v, 1.0 ma i out 400 ma 6.0 v < v in < 26 v , 1.0 ma i out 400 ma 4.90 4.85 5.0 5.0 5.10 5.15 v v output voltage for adjustable option (v o ) v out = v adj (unity gain) 6.5 v < v in < 16 v, 1.0 ma < i out < 400 ma 4.5 v < v in < 26 v , 1.0 ma < i out < 400 ma 1.274 1.261 1.300 1.306 1.326 1.339 v v dropout voltage (v in ? v out ) (5.0 v and adj. > 5.0 v options only) i out = 400 ma i out = 1.0 ma ? ? 400 30 600 150 mv mv load regulation v in = 14 v, 5.0 ma i out 400 ma ? 30 5.0 30 mv line regulation (2.5 v, 3.3 v, and adjustable options) 4.5 v < v in < 26 v, i out = 1.0 ma ? 5.0 25 mv line regulation (5.0 v option) 6.0 v < v in < 26 v, i out = 1.0 ma ? 5.0 25 mv quiescent current, (i q ) active mode i out = 100 a, v in = 12 v, delay = 3.0 v, mon = 3.0 v i out = 75 ma, v in = 14 v, delay = 3.0 v, mon = 3.0 v i out 400 ma, v in = 14 v, delay = 3.0 v, mon = 3.0 v ? ? ? 100 2.5 25 150 5.0 45 a ma ma current limit ? 425 800 ? ma short circuit output current v out = 0 v 100 500 ? ma thermal shutdown (guaranteed by design) 150 180 ? c 3. voltage range specified in the output stage of the electrical characteristics in boldface type.
ncv8504 series http://onsemi.com 4 electrical characteristics (continued) (i out = 1.0 ma, ? 40 c t j 150 c; v in = dependent on voltage option (note 4); unless otherwise specified.) characteristic test conditions min typ max unit reset function (reset ) reset threshold for 2.5 v option high (v rh ) low (v rl ) hysteresis v in = 4.5 v (note 5) (note 6) v out increasing v out decreasing 2.35 2.30 25 ? ? ? 1.0 v o ? ? v v mv reset threshold for 3.3 v option high (v rh ) low (v rl ) hysteresis v in = 4.5 v (note 5) (note 6) v out increasing v out decreasing 3.10 3.00 35 ? ? ? 1.0 v o ? ? v v mv reset threshold for 5.0 v option high (v rh ) low (v rl ) hysteresis v in = 6.0 v (note 6) v out increasing v out decreasing 4.70 4.60 50 ? ? ? 1.0 v o ? ? v v mv reset threshold for adjustable option high (v rh ) low (v rl ) hysteresis v in = 4.5 v (note 5) (note 6) v out increasing v out decreasing 1.22 1.19 10 ? ? ? 1.0 v o ? ? v v mv reset output voltage low (v rlo ) v in = minimum (note 6) (note 7) 1.0 v v out v rl , r reset = 5.1 k ? 0.1 0.4 v delay switching threshold (v dt ) (2.5 v, 3.3 v, and 5.0 v options) v in = minimum (note 6) (note 7) 1.4 1.8 2.2 v delay switching threshold (v dt ) (adjustable option) v in = minimum (note 6) (note 7) 1.0 1.3 1.6 v delay low voltage v in = minimum (note 6) (note 7) v out < reset threshold low(min) ? ? 0.2 v delay charge current v in = minimum (note 6) (note 7) delay = 1.0 v, v out > v rh 2.5 4.0 5.5 a delay discharge current v in = minimum (note 6) (note 7) delay = 1.0 v, v out < v rl 5.0 ? ? ma reset adjust switching voltage (v r(adj) ) hysteresis v in = minimum (note 6) (note 7) increasing and decreasing 1.16 20 1.25 50 1.34 100 v mv flag /monitor monitor threshold increasing and decreasing, v in = minimum (note 6) (note 7) 1.22 1.29 1.36 v hysteresis v in = minimum (note 6) (note 7) 10 35 75 mv input current mon = 2.0 v ? 1.0 0.1 1.0 a output saturation voltage mon = 0 v, i flag = 1.0 ma, v in = minimum (note 6) (note 7) ? 0.1 0.4 v voltage adjust (adjustable output only) input current v adj = 1.25 v ? 0.5 ? 0.5 a 4. voltage range specified in the output stage of the electrical characteristics in boldface type. 5. for v in 4.5 v, a reset = low may occur with the output in regulation. 6. part is guaranteed by design to meet specification over the entire v in voltage range, but is production tested only at the specified v in voltage. 7. minimum v in = 4.5 v for 2.5 v, 3.3 v, and adjustable options. minimum v in = 6.0 v for 5.0 v option.
ncv8504 series http://onsemi.com 5 package pin description, adjustable output pin number pin symbol function 1 v adj voltage adjust. a resistor divider from v out to this lead sets the output voltage. 2 v out 2.0%, 400 ma output. 3 ? 6, 11, 12, 14 nc no connection. 7 v in input voltage. 8 mon monitor. input to comparator. if not needed connect to v out. 9 r adj reset adjust. if not needed connect to ground. 10 delay timing capacitor for reset function. 13 gnd ground. all gnd leads must be connected to ground . 15 reset active reset (accurate to v out 1.0 v) 16 flag open collector output from comparator. note: tentative pinout for sow ? 16 e pad. package pin description, fixed output pin number pin symbol function 1 sense kelvin connection which allows remote sensing of output voltage for improved regulation. if remote sensing is not desired, connect to v out. 2 v out 2.0%, 400 ma output. 3 ? 6, 11, 12, 14 nc no connection. 7 v in input voltage. 8 mon monitor. input to comparator. if not needed connect to v out. 9 r adj reset adjust. if not needed connect to ground. 10 delay timing capacitor for reset function. 13 gnd ground. all gnd leads must be connected to ground . 15 reset active reset (accurate to v out 1.0 v) 16 flag open collector output from comparator. note: tentative pinout for sow ? 16 e pad.
ncv8504 series http://onsemi.com 6 v in reset v out flag r adj delay figure 2. block diagram gnd mon current source (circuit bias) current limit sense error amplifier v bg i bias v bg v bg i bias i bias v bg ? 18 mv i bias + ? + ? + ? + ? + bandgap reference thermal protection 1.8 v (fixed versions) 1.3 v (adjustable version) 4.0 a 15 k adjustable version only v adj fixed versions only sense
ncv8504 series http://onsemi.com 7 typical performance characteristics figure 3. 5 v output voltage vs temperature figure 4. 3.3 v output voltage vs temperature figure 5. 2.5 v output voltage vs temperature figure 6. dropout voltage vs output current 0.01 i out , output current (ma) 50 100 150 200 250 350 400 100 esr ( ) 10 1.0 0.1 0 figure 7. output stability with output voltage change figure 8. output stability with output capacitor change ? 40 v out , output voltage (v) 4.90 temperature ( c) 4.98 5.00 5.08 5.10 ? 20 140 0 20 40 60 80 120 100 v out = 5.0 v v in = 14 v i out = 5.0 ma 4.96 5.06 4.94 5.04 4.92 5.02 160 ? 40 v out , output voltage (v) 3.23 temperature ( c) 3.31 3.33 3.35 ? 20 140 0 20 40 60 80 120 100 v out = 3.3 v v in = 14 v i out = 5.0 ma 3.29 3.27 3.25 160 ? 40 v out , output voltage (v) 2.45 temperature ( c) 2.49 2.50 2.54 2.55 ? 20 140 0 20 40 60 80 120 100 v out = 2.5 v v in = 14 v i out = 5.0 ma 2.48 2.53 2.47 2.52 2.46 2.51 160 300 v in = 14 v c vout = 10 f unstable region stable region 2.5 v 3.3 v 5.0 v 0.1 i out , output current (ma) 50 100 150 200 250 350 400 100 esr ( ) 10 1.0 0 300 5 v version unstable region stable region c vout = 0.1 f unstable region c vout = 33 f* *there is no unstable lower region for the 33 f capacitor 0 0 i out , output current (ma) 50 100 150 200 250 dropout voltage (mv) 400 300 200 100 5 v and adj. > 5 v options only 500 600 125 c 300 350 400 25 c ? 40 c
ncv8504 series http://onsemi.com 8 typical performance characteristics figure 9. quiescent current vs output current figure 10. quiescent current vs output current figure 11. quiescent current vs input voltage 0 i q , quiescent current (ma) 0.0 i out , output current (ma) 0.2 0.4 0.6 0.8 1.0 1.2 2.0 5101520 30 25 +25 c +125 c ? 40 c figure 12. quiescent current vs input voltage 35 40 50 45 1.4 1.6 1.8 0 i q , quiescent current (ma) 0 i out , output current (ma) 10 20 30 40 50 60 50 100 150 200 300 250 +25 c +125 c ? 40 c 350 400 500 450 6 i q , quiescent current (ma) 0 v in , input voltage (v) 2 4 6 8 10 12 8 10 12 14 18 16 t = 25 c i out = 200 ma 20 22 26 24 i out = 100 ma i out = 50 ma i out = 10 ma 6 i q , quiescent current ( a) 0 v in , input voltage (v) 20 40 60 80 100 140 8 10 12 14 18 16 t = 25 c 20 22 26 24 i out = 100 a 120
ncv8504 series http://onsemi.com 9 circuit description regulator control functions the ncv8504 contains the microprocessor compatible control function reset (figure 13). figure 13. reset and delay circuit wave forms v in v out reset delay (v dt ) threshold delay threshold reset t d t d reset function a reset signal (low voltage) is generated as the ic powers up until v out is within 1.5% of the regulated output voltage, or when v out drops out of regulation,and is lower than 4.0% below the regulated output voltage. hysteresis is included in the function to minimize oscillations. the reset output is an open collector npn transistor, controlled by a low voltage detection circuit. the circuit is functionally independent of the rest of the ic thereby guaranteeing that the reset signal is valid for v out as low as 1.0 v. adjustable reset function the reset threshold can be made lower by connecting an external resistor divider to the r adj lead from the v out lead, as displayed in figure 14. this lead is grounded to select the default value of 4.6 v (on the 5.0 v option). figure 14. adjustable reset r adj to p and system power r rst v out c out reset c delay delay ncv8504 to p and reset port v r(adj) delay function the reset delay circuit provides a programmable (by external capacitor) delay on the reset output lead. the delay lead provides source current (typically 4.0 a) to the external delay capacitor during the following proceedings: 1. during power up (once the regulation threshold has been verified). 2. after a reset event has occurred and the device is back in regulation. the delay capacitor is discharged when the regulation (reset threshold) has been violated. this is a latched incident. the capacitor will fully discharge and wait for the device to regulate before going through the delay time event again. flag /monitor comparator a general use comparator is included whose positive input terminal is tied to the on ? chip bandgap voltage reference. this provides a very temperature stable referenced comparator with versatile use in any system. the trip point can be programmed externally using a resistor divider to the input monitor (mon) (figure 15). the typical threshold is 1.29 v on the mon pin. figure 15. flag/monitor function v bat v in mon v out c out v cc i/o reset p flag reset gnd delay ncv8504 r adj v mon voltage adjust figure 16 shows the device setup for a user configurable output voltage. the feedback to the v adj pin is taken from a voltage divider referenced to the output voltage. the loop is balanced around the unity gain threshold (1.30 v typical). figure 16. adjustable output voltage v out v adj ncv8504 15 k 5.1 k c out 5.0 v 1.28 v
ncv8504 series http://onsemi.com 10 application notes flag monitor figure 17 shows the flag monitor waveforms as a result of the circuit depicted in figure 15. as the input voltage falls (v mon ), the monitor threshold is crossed. this causes the voltage on the flag output to go low. figure 17. flag monitor circuit waveform v mon mon flag monitor ref. voltage flag setting the delay time the delay time is controlled by the reset delay low voltage, delay switching threshold, and the delay charge current. the delay follows the equation: t delay c delay (v dt reset delay low voltage) delay charge current example: using c delay = 33 nf. assume reset delay low voltage = 0. use the typical value for v dt = 1.8 v (2.5 v, 3.3 v, and 5.0 v options). use the typical value for delay charge current = 4.2 a. t delay 33 nf(1.8 0) 4.2 a 14 ms stability considerations the output or compensation capacitor helps determine three main characteristics of a linear regulator: start ? up delay, load transient response and loop stability. the capacitor value and type should be based on cost, availability, size and temperature constraints. a tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero esr can cause instability. the aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures ( ? 25 c to ? 40 c), both the value and esr of the capacitor will vary considerably. the capacitor manufacturers data sheet usually provides this information. the value for the output capacitor c out shown in figure 18 should work for most applications, however it is not necessarily the optimized solution. figure 18. test and application circuit showing output compensation v in v out c out ** 33 f r rst reset c in * 0.1 f ncv8504 *c in required if regulator is located far from the power supply filter **c out required for stability. capacitor must operate at minimum temperature expected calculating power dissipation in a single output linear regulator the maximum power dissipation for a single output regulator (figure 19) is: p d(max) [v in(max) v out(min) ]i out(max) (1) v in(max) i q where: v in(max) is the maximum input voltage, v out(min) is the minimum output voltage, i out(max) is the maximum output current for the application, and i q is the quiescent current the regulator consumes at i out(max) . once the value of p d(max) is known, the maximum permissible value of r ja can be calculated: (2) r ja 150 o c t a p d the value of r ja can then be compared with those in the package section of the data sheet. those packages with r ja ?s less than the calculated value in equation 2 will keep the die temperature below 150 c. in some cases, none of the packages will be sufficient to dissipate the heat generated by the ic, and an external heatsink will be required. smart regulator ? i q control features i out i in figure 19. single output regulator with key performance parameters labeled v in v out }
ncv8504 series http://onsemi.com 11 figure 20. 16 lead sow (exposed pad), ja as a function of the pad copper area (2 oz. cu thickness), board material = 0.0625 g ? 10/r ? 4 40 70 90 100 thermal resistance, junction to ambient, r ja , ( c/w) 0 copper area (mm 2 ) 200 400 800 80 60 50 600 heat sinks a heat sink effectively increases the surface area of the package to improve the flow of heat away from the ic and into the surrounding air. each material in the heat flow path between the ic and the outside environment will have a thermal resistance. like series electrical resistances, these resistances are summed to determine the value of r ja : r ja r jc r cs r sa (3) where: r jc = the junction ? to ? case thermal resistance, r cs = the case ? to ? heatsink thermal resistance, and r sa = the heatsink ? to ? ambient thermal resistance. r jc appears in the package section of the data sheet. like r ja , it too is a function of package type. r cs and r sa are functions of the package type, heatsink and the interface between them. these values appear in heat sink data sheets of heat sink manufacturers. ordering information device output voltage package shipping ? ncv8504pwadjg adjustable sow ? 16 exposed pad (pb ? free) 47 units/rail ncv8504pwadjr2g sow ? 16 exposed pad (pb ? free) 1000 tape & reel ncv8504pw25g 2.5 v sow ? 16 exposed pad (pb ? free) 47 units/rail NCV8504PW25R2G sow ? 16 exposed pad (pb ? free) 1000 tape & reel ncv8504pw33g 3.3 v sow ? 16 exposed pad (pb ? free) 47 units/rail ncv8504pw33r2g sow ? 16 exposed pad (pb ? free) 1000 tape & reel ncv8504pw50g 5.0 v sow ? 16 exposed pad (pb ? free) 47 units/rail ncv8504pw50r2g sow ? 16 exposed pad (pb ? free) 1000 tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d.
ncv8504 series http://onsemi.com 12 package dimensions soic 16 lead wide body exposed pad pdw suffix case 751ag ? 01 issue a g ? w ? ? u ? p m 0.25 (0.010) w ? t ? seating plane k d 16 pl c m 0.25 (0.010) t uw s s m f detail e detail e r x 45 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable protrusion shall be 0.13 (0.005) total in excess of the d dimension at maximum material condition. 6. 751r-01 obsolete, new standard 751r-02. j m 14 pl pin 1 i.d. 8 1 16 9 top side 0.10 (0.004) t 16 exposed pad 18 back side l h dim a min max min max inches 10.15 10.45 0.400 0.411 millimeters b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc h 3.45 3.66 0.136 0.144 j 0.25 0.32 0.010 0.012 k 0.00 0.10 0.000 0.004 l 4.72 4.93 0.186 0.194 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 a b 9 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* 0.350 0.175 0.050 0.376 0.188 0.200 0.074 dimensions: inches 0.024 0.150 exposed pad c l c l on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncv8504/d smart regulator is a registered trademark of semiconductor components industries, llc (scillic). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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